1. Field of the Invention
The present invention relates generally to a packaging substrate structure and a manufacturing method thereof, and more particularly, to a packaging substrate structure, circuit layer of which has a large-dimension conductive block, and a manufacturing method of the packaging substrate structure.
2. Description of Related Art
Owing to the flourishing development of the electronics industry, the research and development of electronic products have a trend toward multi-function, high-performance products. To satisfy the packaging requirements of high integration and miniaturization for semiconductor packages, multi-layer packaging substrates are developed, wherein dielectric layers and circuit layers are formed on the surface of a core substrate, and conductive vias are formed in the dielectric layers for electrical connection between the circuit layers.
Besides general circuits, circuits of a multi-layer packaging substrate can further comprise a large-dimension conductive block for power connection or ground connection. FIGS. 1A to 1F show a manufacturing method of such a multi-layer packaging substrate.
As shown in FIG. 1A, a carrier layer 10 having a plurality of circuits 101 and electrical connection terminals 102, 102′ disposed on the surface thereof is provided. The carrier layer 10 is one of a core board and a dielectric layer of a multi-layer packaging substrate.
As shown in FIG. 1B, a dielectric layer 11 is formed on the surfaces of the carrier layer 10, the circuit layer 101 and the electrical connection terminals 102, 102′. A plurality of first vias 110, 110′ are formed in the dielectric layer 11 to expose surfaces of the electrical connection terminals 102, 102′.
As shown in FIG. 1C, a conductive seed layer 13 is formed on the dielectric layer 11.
As shown in FIG. 1D, a resist layer 14 is formed on the conductive seed layer 13, and a plurality of small-dimension opening areas 140 and a large-dimension opening area 140′ are formed in the resist layer 14 to expose a portion of the conductive seed layer 13 on the dielectric layer 11 and to expose the electrical connection terminals 102, 102′.
As shown in FIG. 1E, a first circuit layer 15 is formed through an electroplating process that uses the conductive seed layer 13 as a current conductive path, wherein the first circuit layer 15 comprises first conductive vias 151, 151′ formed in the first vias 110, 110′, first circuits 152 and a large-dimension conductive block 152′ formed in the areas 140, 140′ of the resist layer 14.
As shown in FIGS. 1F and 1F′, the resist layer 14 and the conductive seed layer 13 are removed to expose the first circuits 152 and the conductive block 152′.
However, during formation of the large-dimension conductive block 152′ by electroplating, as the electrical current density of the large-dimension conductive block 152′ is smaller than that of the small-dimension first circuits 152, thickness of the conductive block 152′ can be insufficient and there is a difference e between the thickness of the first circuits 152 and that of the conductive block 152′, and even a hollow center 153 can be formed. Thus, the entire thickness of the first circuit layer 15 becomes uneven. As a result, the dielectric layer of the subsequent formed built-up circuit can have an uneven thickness, which makes the via processing rather difficult and accordingly leads to poor electrical connection and poor impedance control.
Therefore, there is a need to provide a manufacturing method of a circuit layer with a large-dimension conductive block so as to prevent uneven thickness or a hollow center of conductive block caused by the difference of electrical current density distribution between large-dimension and small-dimension opening areas during electroplating.